BEGIN:VCALENDAR
VERSION:2.0
PRODID:Linklings LLC
BEGIN:VTIMEZONE
TZID:Europe/Stockholm
X-LIC-LOCATION:Europe/Stockholm
BEGIN:DAYLIGHT
TZOFFSETFROM:+0100
TZOFFSETTO:+0200
TZNAME:CEST
DTSTART:19700308T020000
RRULE:FREQ=YEARLY;BYMONTH=3;BYDAY=-1SU
END:DAYLIGHT
BEGIN:STANDARD
TZOFFSETFROM:+0200
TZOFFSETTO:+0100
TZNAME:CET
DTSTART:19701101T020000
RRULE:FREQ=YEARLY;BYMONTH=10;BYDAY=-1SU
END:STANDARD
END:VTIMEZONE
BEGIN:VEVENT
DTSTAMP:20220812T074334Z
LOCATION:Foyer 2nd Floor
DTSTART;TZID=Europe/Stockholm:20220628T090000
DTEND;TZID=Europe/Stockholm:20220628T110000
UID:submissions.pasc-conference.org_PASC22_sess181_pos128@linklings.com
SUMMARY:P47 - Performance Modelling of Generated Stencil Kernels within th
 e HyTeG Framework
DESCRIPTION:Poster\n\nP47 - Performance Modelling of Generated Stencil Ker
 nels within the HyTeG Framework\n\nThönnes\n\nIn this work, we present how
  code generation techniques significantly improve the performance of the c
 omputational kernels in the HyTeG framework. This HPC framework combines t
 he performance and memory advantages of matrix-free multigrid solvers with
  the flexibility of unstructured meshes. With the use of the pystencils co
 de generation toolbox, the original abstract C++ kernels are replaced with
  highly optimized loop nests. The performance of one of those kernels (the
  matrix-vector multiplication) is thoroughly analyzed using the Execution-
 Cache-Memory (ECM) performance model. These predictions are validated by m
 easuring execution on the SuperMUC-NG supercomputer. Overall, the results 
 agree with the predicted performance, and the discrepancies are discussed.
  Additionally, we conduct a node-level scaling study which shows the expec
 ted behavior for a memory-bound compute kernel.
END:VEVENT
END:VCALENDAR