Session

DescriptionNowadays, accelerator devices, namely GPUs, are the workhorse for floating point intensive applications, such as machine learning and large computational simulations. Furthermore, these devices are also energy efficient, which is critical for the upcoming exascale era of computation. Reconfigurable hardware such as Field Programmable Gate Arrays (FPGA) present a promising alternative solution for increased performance per watt. The advancement of high-level synthesis techniques combined with well-known parallel programming APIs (e.g., OpenCL) now allows HPC software developers to express program logic, parallelism, and data dependencies, using familiar paradigms as opposed to the traditional Hardware Description Language (e.g. Verilog, VHDL) approach typically more suited to hardware designers. The goal of the minisymposium is to gather researchers and developers to discuss their experiences with application development on FPGA devices. It will serve to review the current state-of-the-art and trends of developments in this domain by engaging with experts in the field, facilitating knowledge transfer and possible collaborations. Speakers will be requested to describe their experience, the implemented techniques, and the eventual new developments, which will cover a wide range of perspectives, including those from domain scientists and technical engineers.